CARDIFF: Diffusion Forecasting Acceleration
Identified forecast samples as a new axis for activation
reuse, reducing redundant computation in diffusion
forecasting.
Built a framework that schedules reuse across samples and
denoising steps. It decides whether to
recompute activations, retain them on-chip, or spill
and restore them from off-chip memory, subject to
the accelerator’s memory capacity.
Results across four models and five datasets
- Up to 5.25× modeled speedup
- Up to 6.17× modeled energy savings
-
≤0.1% relative MSE degradation
on held-out forecasts
Performance and energy gains are relative to a no-reuse
baseline. Evaluation uses Timeloop/Accelergy, with additional
compute validation using SCALE-Sim and memory-timing checks.
Diffusion forecasting
Activation reuse
Systolic accelerators
Memory scheduling
Algorithm–Architecture Co-Design of a ConvLSTM Accelerator
for Human Activity Recognition
Designed FPGA acceleration techniques for human activity
recognition using hidden-state reuse, Compute-in-Reorder,
and gate-level parallelism to reduce inference latency
and energy consumption.
ConvLSTM
FPGA
Accelerator RTL
Human activity recognition
Authors:
Keerthivasan Vijayakumar,
Abarajithan Gnaneswaran, Jiayun Zhang, Xiyuan Zhang,
Rajesh K. Gupta, Patrick Pannuto, Ryan Kastner
Hybrid CNN–LNN for Accurate Fall Detection
Developing a co-design approach using ternary weights
(−1, 0, 1), label-aware segmentation, and early exits
for efficient fall detection on edge devices.
CNN–LNN
Ternary weights
Early exits
Fall detection
In progress
Authors:
Keerthivasan Vijayakumar,
Raymond Duenas, Patrick Pannuto, Rajesh K. Gupta
Within-Camera Multilayer Perceptron: DVS Denoising
Pipelined, low-power ASIC acceleration of a multilayer
perceptron for denoising event-camera data.
CVPR 2023 Workshop
Event cameras
ASIC
Paper
·
Code
Authors:
Antonio Rios-Navarro, Shasha Guo, Abarajithan Gnaneswaran,
Keerthivasan Vijayakumar,
Alejandro Linares-Barranco, Thea Aarrestad,
Ryan Kastner, Tobi Delbruck
